(1) Field of the Invention
The invention relates to a method of fabricating semiconductor structures, and more particularly, to the formation of gate oxides of different thicknesses on a silicon substrate in the manufacture of integrated circuit devices.
(2) Description of the Prior Art
Ultra Large-Scale Integration (ULSI) technology has advanced to a point where the smallest, highest speed MOS devices have very thin gate oxides (less than 50 Angstroms). In the current technology, the voltage supply to these high speed devices is typically limited to just above 3 volts. This limitation is imposed to minimize switching times and because the very thin gate oxides could easily be damaged by a higher supply voltage.
This low voltage limitation is not adequate to the input/output (I/O) requirements of the integrated circuit. Many devices external to the integrated circuit operate in a 5 volt regime. Therefore, the very thin gate oxide technology is not sufficient to provide the (I/O) capability required for a most cost efficient integrated circuit.
Techniques have been developed to fabricate both a very thin (less than 50 Angstroms) gate oxide and a thicker (greater than 50 Angstrom) gate oxide on the same circuit. Application of these techniques allows the integrated circuit designer to provide both state of the art speed and packing density and necessary I/O on the same circuit.
Referring to FIG. 1, a cross-section of a partially completed prior art integrated circuit device is shown. A silicon substrate 10 is shown. A shallow trench isolation (STI) 14 is formed in the silicon substrate 10. The silicon substrate 10 is divided into two parts as indicated by the dash lines. The low voltage section 18 of the silicon substrate 10 will require the very thin oxide. The high voltage section 22 of the silicon substrate 10 will require the thicker oxide.
Referring now to FIG. 2, a first gate oxide layer 26 is grown overlying the silicon substrate 10 on both the low voltage section 18 and the high voltage section 22. The first gate oxide layer 26 is grown to a thickness somewhat greater than will be needed by the high voltage section 22. In this example, approximately 80 Angstroms of silicon dioxide is grown in the first gate oxide layer 26.
Referring now to FIG. 3, a photoresist layer 30 is deposited overlying the first gate oxide layer 26. The photoresist layer 30 is patterned to expose the first gate oxide layer 26 overlying the low voltage section 18.
Referring now to FIG. 4, the exposed first gate oxide layer 26 is etched away. Because of the thickness of the oxide, a buffered oxide etch (BOE) is used as is conventional in the art.
Referring to FIG. 5, the photoresist layer 30 is now stripped away. The strip may be by plasma stripping (ashing) or by a wet strip.
Referring now to FIG. 6, a pre-gate clean typically is performed. The purpose of the pre-gate clean is to purge the silicon surface of any remaining contaminants from the BOE etch and to prepare the surface for thermal oxidation of a high quality gate oxide. During the pre-gate clean step, the thickness of the thicker gate oxide layer 26 overlying the high voltage section 22 is reduced. In this example, the thicker gate oxide layer 26 remaining after the clean is about 60 Angstroms.
Referring now to FIG. 7, a thermal gate oxidation is performed. A very thin gate oxide layer 34 is grown overlying the low voltage section 18. Approximately 30 Angstroms of silicon dioxide is grown. Meanwhile, the thicker gate oxide layer increases in thickness to a final value of about 65 Angstroms.
While the prior art technique does create gate oxide layers of different thicknesses suitable for low and high voltage circuits, it has several disadvantages. First, because the photoresist layer 30 is coated directly over the thicker gate oxide layer 26, the quality of the thicker gate oxide layer 26 is jeopardized. Second, the buffered oxide etch that must be used to etch away the relatively thick first gate oxide layer 26, is more difficult to control than, for example, a pre-gate clean. Damage to the silicon substrate 10 in the low voltage section 18 may result. This damage is detrimental to the formation of a very high quality oxide. Finally, exposure of the silicon substrate 10 to the photoresist stripping process, whether plasma or wet etch, can damage the silicon substrate 10. Again, this can cause problems for the silicon dioxide gate that will be grown there.
Several prior art approaches disclose methods to form gate oxides of different thicknesses in the fabrication of integrated circuits. U.S. Pat. No. 5,502,009 to Lin discloses a process to fabricate gate oxides of different thicknesses. The first embodiment grows a common thin gate oxide over both low voltage sections and high voltage sections. Silicon nitride is deposited, patterned, and used as a hard mask to etch away the thin gate oxide layer from the high voltage section. A thick gate oxide is then grown over the high voltage section. The silicon nitride is then etched away. In the second embodiment, a silicon dioxide layer is added overlying the silicon nitride layer. This silicon dioxide layer is patterned and to form a hard mask for etching the silicon nitride layer. In both embodiments, only the thicker gate oxide is re-grown. The thin gate oxide that is grown at the beginning of the sequence is not re-grown. U.S. Pat. No. 5,057,449 to Lowrey et al teaches a process to create gate oxides of different thicknesses for DRAMs. Prior to field oxidation, a thick gate oxide is grown. This oxide is patterned using photoresist. The photoresist is stripped, and the thin gate oxide layer is grown. A silicon nitride layer is used to shield the thin and thick gate oxides during subsequent field oxidation. U.S. Pat. No. 5,882,993 to Gardner et al discloses a process to form gate oxides of different thicknesses. A nitrogen impurity concentration is introduced into selective portions of the silicon substrate. During the gate oxide thermal oxidation, silicon dioxide grows more slowly over nitrogen-rich areas of silicon. U.S. Pat. No. 5,668,035 to Fang et al teaches a process to form gate oxides of different thicknesses for DRAM applications. A thick gate oxide is grown over logic and DRAM sections. Polysilicon is deposited and patterned. The gate oxide is etched away from the logic areas using the polysilicon layer as a mask. A thin gate oxide is then grown over the logic sections. U.S. Pat. No. 5,716,863 to Arai discloses a process to create gate oxides of different thicknesses using a polysilicon mask layer.